A key requirement in many applications, ranging from video to communications, is large waveform generation and acquisition. Video test image generation with AWGs, sparkle code test of ADCs with digital waveform generators/analyzers, and error vector magnitude (EVM) measurements of baseband modulators/demodulators with digitizers are some of the myriad of applications requiring deep memory for waveform capture and generation.
The SMC input and output data transfer cores are designed to arbitrate waveform movements between the memory banks and the front-end electronics of the instrument at 100 MHz. Incorporated into the SMC, along with the DSF, is the National Instruments SCARAB memory controller, which provides the interface between the memory banks, the DSF, and the National Instruments MITE, a scatter-gather DMA controller. The SCARAB effectively keeps track of where waveforms and instructions are stored in memory and fetches the appropriate data upon request from the DSF and the MITE. It also provides the capability to stream waveforms to and from the memory at the full sampling rates at a sustained pace to accommodate large waveform acquisition and generation. The SMC input core treats the deep memory as a 2-port FIFO buffer, whereby it moves the data at the full sampling rate of 100 MHz from the ADC of the digitizer or the digital lines of the digital waveform generator/analyzer into the memory banks and streams data to the host PC at the available bandwidth of the PCI bus.
The SMC output core treats the memory in a relatively more complex manner because of the shared data and instruction format of the memory. It has to stream data to the digital-to-analog converter (DAC) of the AWG or the digital lines of the digital waveform generator/analyzer at the full sampling rate of 100 MHz, meanwhile extracting the instructions for sequencing the output waveforms at a rate whereby the full sampling rate of 100 MHz is guaranteed. Because of potentially large sequences ranging into hundreds of thousands of instructions, it is not possible to compile all of the sequencing instructions in the DSF at the start of generation due to FPGA size constraints. Therefore, the SCARAB has not only to pull out waveforms from the deep memory at the full sampling rate of 100 MHz but also to provide the sequence instructions to the DSF to execute in real time.
The SMC input and output data transfer cores are designed to arbitrate waveform movements between the memory banks and the front-end electronics of the instrument at 100 MHz. Incorporated into the SMC, along with the DSF, is the National Instruments SCARAB memory controller, which provides the interface between the memory banks, the DSF, and the National Instruments MITE, a scatter-gather DMA controller. The SCARAB effectively keeps track of where waveforms and instructions are stored in memory and fetches the appropriate data upon request from the DSF and the MITE. It also provides the capability to stream waveforms to and from the memory at the full sampling rates at a sustained pace to accommodate large waveform acquisition and generation. The SMC input core treats the deep memory as a 2-port FIFO buffer, whereby it moves the data at the full sampling rate of 100 MHz from the ADC of the digitizer or the digital lines of the digital waveform generator/analyzer into the memory banks and streams data to the host PC at the available bandwidth of the PCI bus.
The SMC output core treats the memory in a relatively more complex manner because of the shared data and instruction format of the memory. It has to stream data to the digital-to-analog converter (DAC) of the AWG or the digital lines of the digital waveform generator/analyzer at the full sampling rate of 100 MHz, meanwhile extracting the instructions for sequencing the output waveforms at a rate whereby the full sampling rate of 100 MHz is guaranteed. Because of potentially large sequences ranging into hundreds of thousands of instructions, it is not possible to compile all of the sequencing instructions in the DSF at the start of generation due to FPGA size constraints. Therefore, the SCARAB has not only to pull out waveforms from the deep memory at the full sampling rate of 100 MHz but also to provide the sequence instructions to the DSF to execute in real time.
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